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Allwinner /D1H /UART[5] /HSK

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Interpret as HSK

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https://regviz.com/r/Allwinner/D1H/UART[4]/HSK#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0hsk

Description

UART DMA Handshake Configuration Register

Fields

hsk

Handshake configuration

165 (wait_cycle): undefined

229 (handshake): undefined

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data